The heart of the classic D/A converter design is a resistor network configuration known as an R2R ladder. Precision resistor processes are capable of sufficient tolerance to exceed 16 bits accuracy (i.e. 0.00076%). However, in the process of completing the DAC design by adding the digital switches (typically FETS), accuracy is lost and limited. Practical circuit implementations of the D/A converter utilizing R2R ladders are 1) scaling the switch sizes in a binary-weighted fashion and 2) decoding the MSBs into segments of resistor value R. Even with these techniques, the best D/A converters still only achieve 12 to 13 bits linearity accuracy.
There are other D/A converters that have a resistor ladder configuration which greatly reduces the switch's ill effect and increases the accuracy of the D/A converter. These circuits reduce the effect of the ON resistance of the FETs by enlarging the serial resistance. However, its speed is deteriorated as the serial resistance gets larger. Thus, there is always a trade-off between the speed and accuracy with these types of D/A converters.
Therefore, a need exists to provide a circuit and method to overcome the above problem. The circuit will be a small-area D/A converter that is low-power, has a high-resolution, and medium-speed that can be realized using a precision resistor process to exceed 16 bits accuracy.